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2010-2012 Microchip Technology Inc.

DS39977F-page 157

PIC18F66K80 FAMILY

10.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are six Peripheral

Interrupt Enable registers (PIE1 through PIE6). When

IPEN (RCON<7>) = 0, the PEIE bit must be set to

enable any of these peripheral interrupts.

REGISTER 10-9:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE

ADIE

RC1IE

TX1IE

SSPIE

TMR1GIE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PSPIE:

Parallel Slave Port Read/Write Interrupt Enable bit

= Enables the PSP read/write interrupt

= Disables the PSP read/write interrupt

bit 6

ADIE:

A/D Converter Interrupt Enable bit

= Enables the A/D interrupt

= Disables the A/D interrupt

bit 5

RC1IE:

EUSARTx Receive Interrupt Enable bit

= Enables the EUSARTx receive interrupt

= Disables the EUSARTx receive interrupt

bit 4

TX1IE:

EUSARTx Transmit Interrupt Enable bit

= Enables the EUSARTx transmit interrupt

= Disables the EUSARTx transmit interrupt

bit 3

SSPIE:

Master Synchronous Serial Port Interrupt Enable bit

= Enables the MSSP interrupt

= Disables the MSSP interrupt

bit 2

TMR1GIE:

TMR1 Gate Interrupt Enable bit

= Enables the gate

= Disabled the gate

bit 1

TMR2IE:

TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE:

TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

= Disables the TMR1 overflow interrupt

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